- BSc in Computer science/ Electrical engineering from known University- Must.
- Strong background in signal processing and/or communications protocols-Must. (Eth/Pcie etc)
- AT least 3-5 years experience as VLSI Design Eng with Verilog- Must.
- Experience with synthesis and STA (Static Timing Analysis) -Advantage.
- Experienced in implementation of complex communication IP – Advantage. (CPU/DSP/Mctrl)
- understanding of fix point implementation, modulation, coding, detection, equalization, timing/phase recovery – Advantage.
- C,C++, SystemC – Advantage.
- VLSI design engineer that will join Company Design group
- Taking part in the architecture and implementation of complex:Wireless Networking IPs OR physical layer (PHY) transceiver channels
- Working closely with Company system team developing together high end DSP and Networking IPs.